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R1LV1616HBG-I Series
Wide Temperature Range Version 16 M SRAM (1-Mword x 16-bit)
REJ03C0263-0100 Rev.1.00 Sep.21.2005
Description
The R1LV1616HBG-I Series is 16-Mbit static RAM organized 1-Mword x 16-bit. R1LV1616HBG-I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48-ball plastic FBGA for high density surface mounting.
Features
* Single 3.0 V supply: 2.7 V to 3.6 V * Fast access time: 45/55 ns (max) * Power dissipation: Active: 9 mW/MHz (typ) Standby: 1.5 W (typ) * Completely static memory. No clock or timing strobe required * Equal access and cycle times * Common data input and output. Three state output * Battery backup operation. 2 chip selection for battery backup * Temperature range: -40 to +85C
Ordering Information
Type No. R1LV1616HBG-4SI R1LV1616HBG-5SI Access time 45 ns 55 ns Package 48-ball plastic FBGA with 0.75 mm ball pitch PTBG0048HF (48FHJ)
Rev.1.00, Sep.21.2005, page 1 of 13
R1LV1616HBG-I Series
Pin Arrangement
48-ball FBGA
1 A
LB#
2
OE#
3
A0
4
A1
5
A2
6
CS2
B
I/O8
UB#
A3
A4
CS1#
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
VSS
I/O11
A17
A7
I/O3
VCC
E
VCC
I/O12
VSS
A16
I/O4
VSS
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
A19
A12
A13
WE#
I/O7
H
A18
A8
A9
A10
A11
NU
(Top view)
Pin Description
Pin name A0 to A19 Address input I/O0 to I/O15 Data input/output CS1# (CS1) Chip select 1 CS2 Chip select 2 WE# (WE) Write enable OE# (OE) Output enable LB# (LB) Lower byte select UB# (UB) Upper byte select VCC Power supply VSS Ground NU*1 Not used (test mode pin) Note: 1. This pin should be connected to a ground (VSS), or not be connected (open). Function
Rev.1.00, Sep.21.2005, page 2 of 13
R1LV1616HBG-I Series
Block Diagram
LSB A19 A8 A9 A10 A11 A12 A13 A14 A16 A18 A15 A3 MSB A6 V CC V SS
Row decoder
* * * * *
Memory matrix 8,192 x 128 x 16
I/O0 Input data control I/O15
* *
Column I/O Column decoder
* *
MSB A17 A7 A5 A4 A2 A1 A0 LSB
* *
CS2 CS1# LB# UB# WE# OE#
Control logic
Rev.1.00, Sep.21.2005, page 3 of 13
R1LV1616HBG-I Series
Operation Table
CS1# CS2 WE# OE# H x x x x L x x x x x x L H H L L H H L L H H L L H L x L H L x L H L x L H H H Note: H: VIH, L: VIL, x: VIH or VIL UB# x x H L H L L H L x LB# x x H L L H L L H x I/O0 to I/O7 High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z High-Z I/O8 to I/O15 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable
Absolute Maximum Ratings
Parameter Power supply voltage relative to VSS Terminal voltage on any pin relative to VSS Power dissipation Storage temperature range Storage temperature range under bias Notes: 1. VT min: -2.0 V for pulse half-width 10 ns. 2. Maximum voltage is +4.6 V. Symbol VCC VT PT Tstg Tbias Value -0.5 to +4.6 -0.5*1 to VCC + 0.3*2 1.0 -55 to +125 -40 to +85 Unit V V W C C
DC Operating Conditions
Symbol Supply voltage VCC VSS Input high voltage VIH Input low voltage VIL Ambient temperature range Ta Note: 1. VIL min: -2.0 V for pulse half-width 10 ns. Parameter Min 2.7 0 2.2 -0.3 -40 Typ 3.0 0 Max 3.6 0 VCC + 0.3 0.6 +85 Unit V V V V C Note
1
Rev.1.00, Sep.21.2005, page 4 of 13
R1LV1616HBG-I Series
DC Characteristics
Parameter Input leakage current Output leakage current Symbol |ILI| |ILO| Min Typ Max 1 1 Unit Test conditions A Vin = VSS to VCC A CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC mA CS1# = VIL, CS2 = VIH, Others = VIH/ VIL, II/O = 0 mA mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, WE# = VIH, Others = VIH/VIL mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL mA Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, WE# = VIH, Others = VIH/VIL Address increment scan or decrement scan mA Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL Address increment scan or decrement scan Cycle time = 1 s, duty = 100%, II/O = 0 mA, CS1# 0.2 V, CS2 VCC - 0.2 V VIH VCC - 0.2 V, VIL 0.2 V CS2 = VIL 0 V Vin (1) 0 V CS2 0.2 V or (2) CS1# VCC - 0.2 V, CS2 VCC - 0.2 V or (3) LB# = UB# VCC - 0.2 V, CS2 VCC - 0.2 V, CS1# 0.2 V Average value IOH = -1 mA IOH = -100 A IOL = 2 mA IOL = 100 A
Operating current Average operating current
ICC ICC1 (READ) ICC1

22*
1
20 35
30*1
50
ICC2 (READ)
3*
1
8
ICC2
20*1
30
ICC3
3*1
8
mA
Standby current
ISB ISB1

0.1*1 0.5*
1
0.5 8
mA A
VOH 2.4 V VOH VCC - 0.2 V Output low voltage VOL 0.4 V VOL 0.2 V Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. Output high voltage
Rev.1.00, Sep.21.2005, page 5 of 13
R1LV1616HBG-I Series
Capacitance
(Ta = +25C, f = 1.0 MHz)
Parameter Symbol Min Typ Input capacitance Cin Input/output capacitance CI/O Note: 1. This parameter is sampled and not 100% tested. Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1
AC Characteristics
(Ta = -40 to +85C, VCC = 2.7 V to 3.6 V) Test Conditions * * * * Input pulse levels: VIL = 0.4 V, VIH = 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.4 V Output load: See figures (Including scope and jig)
1.4 V
RL=500 Dout 50pF
Rev.1.00, Sep.21.2005, page 6 of 13
R1LV1616HBG-I Series Read Cycle
R1LV1616HBG-I -4SI -5SI Max Min Max 55 45 55 45 55 45 55 30 35 10 45 55 10 10 5 5 20 0 20 20 0 20 15 0 20 15 0 20
Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z LB#, UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#, UB# disable to high-Z Output disable to output in high-Z
Symbol tRC tAA tACS1 tACS2 tOE tOH tBA tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ
Min 45 10 10 10 5 5 0 0 0 0
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
2, 3 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Write Cycle
R1LV1616HBG-I -4SI -5SI Parameter Symbol Min Max Min Max Unit Notes Write cycle time tWC 45 55 ns Address valid to end of write tAW 45 50 ns Chip selection to end of write tCW 45 50 ns 5 Write pulse width tWP 35 40 ns 4 LB#, UB# valid to end of write tBW 45 50 ns Address setup time tAS 0 0 ns 6 Write recovery time tWR 0 0 ns 7 Data to write time overlap tDW 25 25 ns Data hold from write time tDH 0 0 ns Output active from end of write tOW 5 5 ns 2 Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2 Write to output in high-Z tWHZ 0 15 0 20 ns 1, 2 Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
Rev.1.00, Sep.21.2005, page 7 of 13
R1LV1616HBG-I Series
Timing Waveform
Read Cycle
t RC Address tAA tACS1 CS1# tCLZ1 tCHZ1 Valid address
CS2
tACS2 tCLZ2 tCHZ2 tBHZ tBA
LB#, UB# tBLZ tOE OE# tOLZ Dout High impedance Valid data tOH tOHZ
Rev.1.00, Sep.21.2005, page 8 of 13
R1LV1616HBG-I Series Write Cycle (1) (WE# Clock)
tWC Address Valid address tWR
tCW CS1# tCW CS2 tBW LB#, UB# tAW tWP WE# tAS tDW Din tWHZ Valid data
tDH
tOW High impedance
Dout
Rev.1.00, Sep.21.2005, page 9 of 13
R1LV1616HBG-I Series Write Cycle (2) (CS1#, CS2 Clock, OE# = VIH)
tWC Address tAS CS1# tAS CS2 tBW LB#, UB# tCW Valid address tAW tCW tWR
tWP WE#
tDW Din Valid data
tDH
Dout
High impedance
Rev.1.00, Sep.21.2005, page 10 of 13
R1LV1616HBG-I Series Write Cycle (3) (LB#, UB# Clock, OE# = VIH)
tWC Address Valid address tAW tCW CS1# tCW CS2 tAS UB# (LB#) tBW LB# (UB#) tBW tWR
tWP WE# tDW Din-UB (Din-LB) Valid data tDW Valid data tDH tDH
Din-LB (Din-UB) Dout
High impedance
Rev.1.00, Sep.21.2005, page 11 of 13
R1LV1616HBG-I Series
Low VCC Data Retention Characteristics
(Ta = -40 to +85C)
Parameter VCC for data retention Symbol VDR Min 1.5 Typ Max 3.6 Unit V Test conditions*2 Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 VCC - 0.2 V, CS1# VCC - 0.2 V or (3) LB# = UB# VCC - 0.2 V, CS2 VCC - 0.2 V, CS1# 0.2 V VCC = 3.0 V, Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 VCC - 0.2 V, CS1# VCC - 0.2 V or (3) LB# = UB# VCC - 0.2 V, CS2 VCC - 0.2 V, CS1# 0.2 V Average value See retention waveforms
Data retention current
ICCDR
0.5*1
8
A
Chip deselect to data retention time Operation recovery time
tCDR tR
0 5

ns ms
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 VCC - 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state.
Rev.1.00, Sep.21.2005, page 12 of 13
R1LV1616HBG-I Series Low VCC Data Retention Timing Waveform (1) (CS1# Controlled)
t CDR V CC 2.7 V Data retention mode tR
2.2 V V DR CS1# 0V CS1# VCC - 0.2 V
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
t CDR V CC 2.7 V CS2 V DR 0.6 V 0V 0 V < CS2 < 0.2 V Data retention mode tR
Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled)
t CDR V CC 2.7 V Data retention mode tR
2.2 V V DR LB#, UB# 0V LB#, UB# V CC - 0.2 V
Rev.1.00, Sep.21.2005, page 13 of 13
Revision History
Rev. 0.01 1.00 Date Apr. 29. 2005 Sep. 21. 2005 Page Initial issue Deletion of Preliminary
R1LV1616HBG-I Series Data Sheet
Contents of Modification Description
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